SystemVerilog 验证与 testbench

// 设计侧增强：enum + struct + always_comb
typedef enum logic [1:0] {IDLE, RUN, DONE} state_e;
typedef struct packed {
    logic [31:0] addr;
    logic [31:0] data;
    logic        valid;
} req_t;

always_comb begin
    unique case (state)
        IDLE: next = RUN;
        RUN:  next = DONE;
        DONE: next = IDLE;
    endcase
end

interface simple_bus #(parameter WIDTH = 32) (input logic clk);
    logic          req, gnt;
    logic [WIDTH-1:0] addr, wdata, rdata;
    logic          we;

    modport master (output req, addr, wdata, we, input gnt, rdata);
    modport slave  (input  req, addr, wdata, we, output gnt, rdata);

    // 内建断言：任何时刻 req 与 gnt 不同时拉高
    property p_no_conflict; @(posedge clk) not (req && gnt); endproperty
    a_no_conflict: assert property (p_no_conflict);
endinterface

class packet;
    rand bit [31:0] addr, len;
    rand bit [7:0]  data[];

    // 地址 4 字节对齐且在合法区间、长度 1~64、数组大小等于长度
    constraint c_addr { addr[1:0] == 2'b00; addr inside {[32'h1000:32'h2000]}; }
    constraint c_len  { len inside {[1:64]}; data.size() == len; }

    // 带权重的分布：小包更常见（模拟真实流量）
    constraint c_dist { len dist { [1:8] := 60, [9:32] := 30, [33:64] := 10 }; }
endclass

initial begin
    packet p = new();
    repeat (1000) begin
        assert (p.randomize()) else $fatal("randomize failed");
        drive(p);
    end
end

class cov_collector;
    covergroup cg_bus @(posedge clk);
        cp_kind: coverpoint bus.kind {
            bins read = {READ}; bins write = {WRITE}; bins burst = {BURST};
        }
        cp_len: coverpoint bus.len {
            bins single = {1}; bins small = {[2:8]};
            bins large = {[9:64]}; bins max = {64};
        }
        cx_kind_len: cross cp_kind, cp_len;   // 交叉：读+大包、写+小包等组合
    endgroup
    function new(); cg_bus = new(); endfunction
endclass

// 基本时序算子
//   ##n        延迟 n 个周期
//   ##[m:n]    延迟 m 到 n 个周期
//   |->        重叠蕴含（同拍）
//   |=>        非重叠蕴含（下一拍）
//   throughout 在某信号保持期间持续成立
//   [*n]       重复 n 次

// 例 1：req 拉高后，1~3 拍内必须 ack
property p_req_ack;
    @(posedge clk) disable iff (!rst_n)
    req |-> ##[1:3] ack;
endproperty
a_req_ack: assert property (p_req_ack) else $error("ack timeout");

// 例 2：valid 与 ready 握手后数据必须稳定到 ready 拉高
property p_data_stable;
    @(posedge clk) disable iff (!rst_n)
    (valid && !ready) |=> (valid && $stable(data));
endproperty
a_data_stable: assert property (p_data_stable);

// 例 3：cover 属性用于覆盖率统计
c_burst: cover property (@(posedge clk) burst_start ##1 burst_len > 8);

UVM 组件树（典型结构）：

uvm_test
 └── uvm_env
      ├── agent (master)
      │    ├── sequencer   ← 产生 sequence item
      │    ├── driver      ← 把 item 转成信号
      │    └── monitor     ← 把信号转回 item
      ├── agent (slave)
      ├── scoreboard       ← 比对 DUT 输出与参考模型
      └── coverage collector

class bus_driver extends uvm_driver #(bus_item);
    `uvm_component_utils(bus_driver)
    virtual simple_bus vif;

    task run_phase(uvm_phase phase);
        bus_item tr;
        vif.req <= 0;
        forever begin
            seq_item_port.get_next_item(tr);   // 从 sequencer 取事务
            @(posedge vif.clk);
            vif.req <= 1'b1; vif.addr <= tr.addr;
            vif.wdata <= tr.data; vif.we <= tr.we;
            do @(posedge vif.clk); while (!vif.gnt);   // 等待握手
            vif.req <= 1'b0;
            seq_item_port.item_done();         // 通知 sequencer
        end
    endtask
endclass

class bus_monitor extends uvm_monitor;
    `uvm_component_utils(bus_monitor)
    virtual simple_bus vif;
    uvm_analysis_port #(bus_item) ap;          // 广播给 scoreboard

    task run_phase(uvm_phase phase);
        forever begin
            @(posedge vif.clk);
            if (vif.req && vif.gnt) begin
                bus_item tr = bus_item::type_id::create("tr");
                tr.addr = vif.addr; tr.data = vif.wdata; tr.we = vif.we;
                ap.write(tr);                  // 发给所有订阅者
            end
        end
    endtask
endclass

class bus_scoreboard extends uvm_scoreboard;
    `uvm_component_utils(bus_scoreboard)
    uvm_analysis_imp #(bus_item, bus_scoreboard) imp;
    bit [31:0] mem[bit [31:0]];        // 参考模型：地址到数据的映射

    function void write(bus_item tr);
        if (tr.we) mem[tr.addr] = tr.data;     // 写：更新参考模型
        else if (tr.data !== mem[tr.addr])     // 读：比对
            `uvm_error("SCB", $sformatf("read mismatch @%h: exp %h got %h",
                       tr.addr, mem[tr.addr], tr.data))
    endfunction
endclass

class burst_read_seq extends uvm_sequence #(bus_item);
    `uvm_object_utils(burst_read_seq)
    rand int unsigned num;
    constraint c_num { num inside {[1:16]}; }

    task body();
        bus_item tr;
        repeat (num) begin
            tr = bus_item::type_id::create("tr");
            start_item(tr);
            tr.we = 0;
            tr.randomize() with { addr inside {[32'h1000:32'h1FFF]}; };
            finish_item(tr);
        end
    endtask
endclass

class top_vseq extends uvm_sequence;
    `uvm_object_utils(top_vseq)
    task body();
        cpu_seq c_seq = cpu_seq::type_id::create("c_seq");
        dma_seq d_seq = dma_seq::type_id::create("d_seq");
        fork
            c_seq.start(p_sequencer.cpu_sqr);   // 并行启动两个 agent
            d_seq.start(p_sequencer.dma_sqr);
        join
    endtask
endclass

1. 写验证计划（vplan）：列出所有功能点与对应的覆盖率 bin
2. 搭建 UVM 环境：agent / scoreboard / coverage
3. 跑随机回归（regression）：数千个随机种子并行跑
4. 分析覆盖率报告：找出未覆盖的 bin
5. 针对性写定向测试或加约束
6. 回到 3，直到覆盖率达标
7. 签核：代码覆盖率 + 功能覆盖率 + 断言全部通过

# 用 SymbiYosys 做形式验证（开源方案）：sby -f prop.sby
# prop.sby 内容示例：
#   [tasks]   bmc: depth 20（有界模型检查，20 拍内找反例）; prove（无界证明）
#   [options] mode prove
#   [engines] smtbmc z3（用 Z3 求解器）

# 典型 CI 脚本骨架
iverilog -g2012 -Wall -o sim.vvp tb.sv dut.sv || exit 1
vvp sim.vvp +SEED=$SEED | tee log.txt
grep -q "UVM_ERROR :    0" log.txt || exit 1     # 无错误则通过
grep "Coverage" log.txt                          # 覆盖率报告